The advancement of electronics has been moving towards two extremes in terms of physical scale. Rapid miniaturization of microelectronics according to Moore's law has led to remarkable increases in computing power while at the same time enabling reductions in cost. In parallel, extraordinary progress has been made in the other, relatively less noticed, area of macroelectronics, where electronic devices are integrated over large area substrates with sizes measured in square meters. Current macroelectronics are primarily based on amorphous silicon (a-Si) or polycrystalline silicon (poly-Si) thin film transistors (TFTs) on glass, and are finding important applications in areas, including flat panel display (FPD), solar cells, radiofrequency identification tags (RFIDs), image sensor arrays and digital x-ray imagers.
While the current technology is successful in many perspectives, it is limited in what applications it can address. For example, there has been growing interest in the use of plastic as the substrate for macroelectronics due to plastic's light weight, flexibility, shock resistance and low cost. However, the fabrication of high performance TFTs on plastics has been extremely challenging because all process steps must be carried out below the glass transition temperature of the plastic. Significant efforts have been devoted to search for new materials (such as organics and organic-inorganic hybrids) or new fabrication strategies suitable for TFTs on plastics, but only with limited success. Organic TFTs promise the potential of roll-to-roll fabrication process on plastic substrates, but with only a limited carrier mobility of about 1 cm2/V·s. The limitations posed by materials and/or substrate process temperature (particularly on plastic) lead to low device performance, restricting devices to low-frequency applications. Therefore, applications that require even modest computation, control, or communication functions cannot be addressed by the existing TFT technology.
Individual semiconductor nanowires (NWs) and single walled carbon nanotubes can be used to fabricate nanoscale field effect transistors (FETs) with electronic performance comparable to and in some case exceeding that of the highest-quality single-crystal materials. In particular, carrier mobility of 300 cm2/V·s has been demonstrated for p-Si NWs, 2000-4000 cm2/V·s for n-indium InP NWs and up to 20,000 cm2/V·s for single walled carbon nanotubes. These nanoFETs promise to push Moore's law to the ultimate limit—molecular level—with unprecedented performance.
Critical to the fabrication of nanoscale TFTs that can be applied to glass, plastics and other substrates requiring low process temperatures is a contact doping and annealing process to implant dopant ions into nanowires and to activate the dopant in the source and drain contact regions of the nanowires and to recover any crystal damage due to ion implantation. Plasma immersion ion implantation (PII) is a large-area and high-throughput doping tool, having many inherent advantages over conventional beam ion implantation. When introduced in the late 1980's, the technique was primarily used to enhance the surface mechanical properties of metals. More recently, the technique has been used for semiconductor processing, including formation of ultra-shallow junctions, selective metal deposition, synthesis of silicon-on-insulator substrates (SIMOX and Ion-Cut), hydrogenation of poly-Si TFTs, and for high aspect ratio trench doping. However, PIII has not to the knowledge of the present inventors been applied to the contact doping of TFTs based on nanowire thin films.
In addition, pulsed laser annealing (PLA) processes have been used in the fabrication of a-Si and poly-Si TFTs for active-matrix liquid-crystal display (AMLCD) applications. Pulsed lasers provide rapid heating and cooling of the a-Si and poly-Si films, without causing the underlying substrate to melt. In comparison to PLA, conventional furnace annealing tends to be very slow, has a high thermal budget, and is not compatible with plastic substrates. Alternatively, very rapid thermal annealing (VRTA) processes involve heating periods of the order of 1 second, and require high peak temperatures that are incompatible with low temperature substrates (for example, glass or plastic substrates). In contrast, PLA can yield TFT performance far superior to that achieved by furnace annealing and VRTA.
Rare-gas halogen excimer lasers have typically been used in conventional pulsed laser annealing processes for a-Si and poly-Si films because of their short wavelength in the UV band, and their ability to produce short high-intensity pulses. ArF (193 nm), KrF (248 nm), and XeCl (308 nm) are the gas mixtures most commonly used in these lasers for laser crystallization and annealing of a-Si and poly-Si thin films. Using lasers in the short wavelength (e.g., UV band) is advantageous for a-Si and poly-Si films because these films are highly absorptive in the UV, whereas most glass substrates are not. However, the use of shorter wavelength lasers (e.g., those which emit in the UV light range) is problematic when used with other substrates, such as polymers or plastics, which absorb highly in the UV range and can be thermally damaged (e.g., melt) when exposed to deep UV laser excitation.
The laser fluence also plays an important role in the uniformity of the resulting film following pulsed laser annealing. Typically, conventional laser annealing of a-Si and poly-Si films requires laser fluences on the order of about 250 mJ/cm2 or higher. At laser fluences below about 100 mJ/cm2, for example, the surface of a-Si and poly-Si films is not even melted, and some heating of the films is all that occurs. However, the thermal impact of such high laser fluences again can cause damage to the underlying low temperature substrate material.
Surprisingly, the inventor(s) of the present application have discovered that the melting threshold of nanowires is much lower than that for bulk Si, e.g., a-Si or poly-Si films, which indicates that nanowires (e.g., incorporated in NW thin films) used in NW-TFTs can be effectively doped and annealed using PIII followed by pulsed laser annealing at low laser fluences (e.g., laser fluences less than about 100 mJ/cm2, for example, less than about 50 mJ/cm2, for example, less than about 20 mJ/cm2, e.g., between about 2 to 18 mJ/cm2). Thus, such laser annealing can advantageously be performed using, for example, relatively long wavelength lasers (e.g., using Nd:YAG or Nd:YLF lasers having wavelengths greater than about 400 nm, e.g., greater than about 500 nm, for example) which are compatible with plastic substrates, and/or shorter wavelength lasers (e.g., excimer lasers) at low power settings, thus avoiding the deep thermal impact of UV absorption in polymer (and other low melting point) substrates. Using such PIII doping and pulsed laser annealing techniques, low resistance Ohmic contacts on nanowire transistors can be created (e.g., leading to improved transconductance and/or contact resistance) without using expensive conventional ion implantation and thermal annealing processes which can cause thermal damage to the underlying low temperature (e.g., plastic) substrates.